Electronic circuitry provides complex functionality that is proving ever more useful. In one common form, circuitry is formed on a semiconductor or other substrate using micro-fabrication processing technology. Typically, circuits with small feature dimension sizes are not designed to carry large amounts of current. So long as the voltage range at any given node does not extend outside of its designed range, these currents remain relatively low and the circuitry will typically operate as designed. However, if the voltage range at any given node extends out of its designed range, a condition of Electrical OverStress (EOS) may occur.
For example, most common semiconductor fabrication processes use substrate or bulk semiconductor with different dopants implanted into certain regions of the substrate. These implant regions define unique electrical characteristics that are important or essential for circuit functionality. Thus, EOS experienced at any of the implant regions may adversely impact circuit performance. Another area where EOS may adversely affect performance is in the interlayer dielectrics, which have voltage limitations as well. Driving a circuit outside of its normal operating range can often temporarily disable performance of the circuit, reduce the operational lifetime of the circuit, or even immediately destroy the circuit. EOS can take many forms, but commonly takes the form of Electro Static Discharge (ESD) events.
Many current protection structures have been designed that are suitable for dissipating current to or from corresponding critical circuit nodes in order to provide protection to corresponding circuitry. Conventionally, a more likely source of excess current is on the pads of integrated circuits, where externally generated voltages and currents are applied to the integrated circuit. However, excess current may be experienced at other circuit nodes as well. To deal with the potential of EOS events occurring at a given node, conventional circuits often include current protection structures at or near the circuit node to be protected.
One conventional technique for providing current protection is to use a zener diode in reversed-biased mode between the circuit node to be protected and a current source or sink. When the reverse breakdown voltage of the zener diode is exceeded due to an EOS event, current flows to or from the circuit node through the reverse-biased zener diode in order to mitigate or eliminate harm to the core circuitry.
However, the processes associated with fabrication of a zener diode are not always standard for given process sets. The introduction of non-standard process steps into a process set can be costly.